A one-semester course in modeling of VLSI interconnections

Quantitative understanding of the parasitic capacitances and inductances, and the resultant propagation delays and crosstalk phenomena associated with the metallic interconnections on the very large scale integrated (VLSI) circuits has become extremely important for the optimum design of the state-o...

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Detalles Bibliográficos
Autor principal: Goel, Ashok K., 1953- (-)
Formato: Libro electrónico
Idioma:Inglés
Publicado: New York, NY : Momentum Press [2015]
Colección:EBSCO Academic eBook Collection Complete.
Momentum Press electronic circuits and semiconductor devices collection.
Acceso en línea:Conectar con la versión electrónica
Ver en Universidad de Navarra:https://innopac.unav.es/record=b32529491*spi
Descripción
Sumario:Quantitative understanding of the parasitic capacitances and inductances, and the resultant propagation delays and crosstalk phenomena associated with the metallic interconnections on the very large scale integrated (VLSI) circuits has become extremely important for the optimum design of the state-of-the-art integrated circuits. More than 65 percent of the delays on the integrated circuit chip occur in the interconnections and not in the transistors on the chip. Mathematical techniques to model the parasitic capacitances, inductances, propagation delays, crosstalk noise, and electromigration-i.
Descripción Física:1 recurso electrónico
Formato:Forma de acceso: World Wide Web.
Bibliografía:Incluye referencias bibliográficas e índice.
ISBN:9781606505137