VLSI test principles and architectures design for testability
This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Most up-to-date coverage of design for testability. Coverage of indu...
| Otros Autores: | , , |
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| Formato: | Libro electrónico |
| Idioma: | Inglés |
| Publicado: |
Amsterdam ; Boston :
Elsevier Morgan Kaufmann Publishers
2006.
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| Colección: | The Morgan Kaufmann series in systems on silicon.
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| Acceso en línea: | Conectar con la versión electrónica |
| Ver en Universidad de Navarra: | https://innopac.unav.es/record=b31700780*spi |
Tabla de Contenidos:
- Design for testability / Laung-Terng (L.-T.) Wang, Xiaoqing Wen, and Khader S. Abdel-Hafez
- Logic and fault simulation / Jiun-Lang Huang, James C.-M. Li, and Duncan M. (Hank) Walker
- Test generation / Michael S. Hsiao
- Logic built-in self-test / Laung-Terng (L.-T.) Wang
- Test compression / Xiaowei Li, Kuen-Jong Lee, and Nur A. Touba
- Logic diagnosis / Shi-Yu Huang
- Memory testing and built-in self-test / Cheng-Wen Wu
- Memory diagnosis and built-in self-repair / Cheng-Wen Wu
- Boundary scan and core-based testing / Kuen-Jong Lee
- Analog and mixed-signal testing / Chauchin Su
- Test technology trends in the nanometer age / Kwang-Ting (Tim) Cheng, Wen-Ben Jone, and Laung-Terng (L.-T.) Wang.
