ESD design and synthesis
"The book focuses on both fundamentals of ESD design to construct and integrate a semiconductor chip. It enables ESD engineers to build better products by exploring six key areas- 1) ESD design synthesis 2) I/O design and integration 3) semiconductor chip architecture 4) floor planning 5) power...
| Autor principal: | |
|---|---|
| Formato: | Libro electrónico |
| Idioma: | Inglés |
| Publicado: |
Chichester, West Sussex, U.K. :
Wiley
2011.
|
| Colección: | EBSCO Academic eBook Collection Complete.
ESD series. |
| Acceso en línea: | Conectar con la versión electrónica |
| Ver en Universidad de Navarra: | https://innopac.unav.es/record=b31117119*spi |
| Sumario: | "The book focuses on both fundamentals of ESD design to construct and integrate a semiconductor chip. It enables ESD engineers to build better products by exploring six key areas- 1) ESD design synthesis 2) I/O design and integration 3) semiconductor chip architecture 4) floor planning 5) power bus design and 6) ESD power clamps. The book is well organised and uses a top down approach, starting by looking at the basics. It takes a look at design synthesis, floor planning and ESD design issues. The book analyses the synthesis of device elements, also the synthesis of ESD circuits and functional circuits. In Chapter 5, the synthesis of ESD power clamps is described, followed by coverage on synthesis of power rails with I/O, ESD and pads in Chapter 6. The integration of special function circuits and special issues is helpfully included in the book before more broad ESD design methodioligies are outlined. The important areas of design rule checking, along with design verification methods, are looked at towards the end of the book, and the last chapter provides the reader with knowledge about useful design tools. In many ways this text is unique. There is currently no other book on the market that addresses ESD design synthesis and its relationaship to the characterisation of test structures and technologies. Focuses on practical design techniques, providing good design practices and rules contains essential information on chip floor-planning and architecture that has not been published in a single book before covers up-to-date technology benchmarking and characterisation uses state-of-the-art examples with detailed discussion includes end-of-chapter design and integration problems"-- |
|---|---|
| Descripción Física: | xx, 270 p. : il |
| Formato: | Forma de acceso: World Wide Web. |
| Bibliografía: | Incluye referencias bibliográficas e índice. |
| ISBN: | 9781119991144 |
