| Sumario: | Welcome to the 31st edition of the ACM International Symposium on Physical Design (ISPD). We continue the great tradition established by its thirty predecessors despite the COVID-19 pandemic. ISPD is a premier venue for the dissemination of manuscripts of the highest quality related to the physical design of integrated circuits. ISPD 2022 provides the forum to present leading-edge research results, exchange ideas, and promote research on critical areas related to the physical design of VLSI and other systems. Across the three days of ISPD 2022, we have 6 keynotes; 12 accepted papers; 12 invited talks; two panels on Monday and Wednesday - each with 6 panellists; 3 speakers including Ricardo Reis with longer talks for his commemorative session, and finally the ISPD 2022 contest results. The regular papers in the ISPD 2022 program were selected after a rigorous, month-long, double-blind review process and virtual meetings, by the Technical Program Committee (TPC) members. These papers exhibit the latest advancements in a variety of topics in physical design, including design flow parameter optimization; floorplanning and macro placement; global placement for both conventional 2D as well as 3D ICs; mixed-cell-height placement legalization; well tap placement for analog and mixedsignal designs; a clock tree design methodology for a Bitcoin mining ASIC; routing for technology nodes below 7nm and for 3D ICs; and kernel mapping for deep learning on the Cerebras wafer-scale engine, the largest chip ever built. A number of these papers utilize advanced machine learning and reinforcement learning techniques. The ISPD 2022 program is complemented by invited talks on topics ranging across analog design automation; 3D IC design; packaging; and advanced algorithmic techniques for performance optimization and power minimization such as machine learning and Lagrangian relaxation. Additionally, we have a panel discussing challenges in VLSI routing, and another panel discussing traditional EDA algorithmic approaches and heuristics compared to more recent machine learning techniques. The conference will feature six keynote addresses. The first keynote on Monday is presented by Dean Drako, CEO of Eagle Eye Networks, IC Manage, and Drako Motors. Mr. Drako will deliver the Monday morning keynote address entitled "The Need for Speed: From Electric Supercars to Cloud Bursting for Design," which will compare our industry's drive for speed to electric supercars, then delve into key elements that design and verification teams use to speed the delivery of their products to market. Jean- Philippe Fricker, Chief System Architect at Cerebras Systems, will deliver the Monday afternoon keynote address entitled "The Cerebras CS-2: Designing an AI Accelerator Around the World's Largest 2.6 Trillion Transistor Chip." This keynote will explore how neural networks' rapidly increasing demands for performance and memory benefit from a new architecture with increased performance, discussing the design principles and trade-offs considered in the Cerebras chip architecture.
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