Three-dimensional integrated circuit design
With vastly increased complexity and functionality in the ""nanometer era"" (i.e. hundreds of millions of transistors on one chip), increasing the performance of integrated circuits has become a challenging task. Connecting effectively (interconnect design) all of these chip elem...
| Autor principal: | |
|---|---|
| Otros Autores: | |
| Formato: | Libro electrónico |
| Idioma: | Inglés |
| Publicado: |
Amsterdam ; Boston :
Morgan Kaufmann
c2009.
|
| Edición: | 1st edition |
| Colección: | Morgan Kaufmann series in systems on silicon.
|
| Materias: | |
| Ver en Biblioteca Universitat Ramon Llull: | https://discovery.url.edu/permalink/34CSUC_URL/1im36ta/alma991009627720306719 |
Tabla de Contenidos:
- Front Cover; Three-Dimensional Integrated Circuit Design; Copyright Page; Dedication Page; Contents; Preface; Acknowledgments; Chapter 1: Introduction; Chapter 2: Manufacturing of 3-D Packaged Systems; Chapter 3: 3-D Integrated Circuit Fabrication Technologies; Chapter 4: Interconnect Prediction Models; Chapter 5: Physical Design Techniques for 3-D ICs; Chapter 6: Thermal Management Techniques; Chapter 7: Timing Optimization for Two-Terminal Interconnects; Chapter 8: Timing Optimization for Multiterminal Interconnects; Chapter 9: 3-D Circuit Architectures
- Chapter 10: Case Study: Clock Distribution Networks for 3-D ICsChapter 11: Conclusions; Appendix A: Enumeration of Gate Pairs in a 3-D IC; Appendix B: Formal Proof of Optimum Single Via Placement; Appendix C: Proof of the Two-terminal Via Placement Heuristic; Appendix D: Proof of Condition for Via Placement of Multiterminal Nets; References; Index
