Verification techniques for system-level design
This book will explain how to verify SoC (Systems on Chip) logic designs using "formal? and "semiformal? verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the...
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| Otros Autores: | , |
| Formato: | Libro electrónico |
| Idioma: | Inglés |
| Publicado: |
Amsterdam ; Boston :
Morgan Kaufmann Publishers
c2008.
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| Edición: | 1st edition |
| Colección: | Morgan Kaufmann series in systems on silicon.
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| Materias: | |
| Ver en Biblioteca Universitat Ramon Llull: | https://discovery.url.edu/permalink/34CSUC_URL/1im36ta/alma991009627619006719 |
| Sumario: | This book will explain how to verify SoC (Systems on Chip) logic designs using "formal? and "semiformal? verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in "functional? verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been gaining popularity.For higher design productivity, it is essential to debug desig |
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| Notas: | Description based upon print version of record. |
| Descripción Física: | 1 online resource (251 p.) |
| Bibliografía: | Includes bibliographical references and index. |
| ISBN: | 9781281049643 9786611049645 9780080553139 |
