Skew-tolerant circuit design
As advances in technology and circuit design boost operating frequencies of microprocessors, DSPs and other fast chips, new design challenges continue to emerge. One of the major performance limitations in today's chip designs is clock skew, the uncertainty in arrival times between a pair of cl...
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| Formato: | Libro electrónico |
| Idioma: | Inglés |
| Publicado: |
San Francisco :
Morgan Kaufmann Publishers
c2001.
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| Edición: | 1st edition |
| Colección: | Morgan Kaufmann Series in Computer Architecture and Design
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| Materias: | |
| Ver en Biblioteca Universitat Ramon Llull: | https://discovery.url.edu/permalink/34CSUC_URL/1im36ta/alma991009627108506719 |
Search Result 1
por Harris, David
Publicado 2001
Publicado 2001
Biblioteca Universitat Ramon Llull (Otras Fuentes: Biblioteca Universidad de Navarra)
Libro electrónico
