Skew-tolerant circuit design
As advances in technology and circuit design boost operating frequencies of microprocessors, DSPs and other fast chips, new design challenges continue to emerge. One of the major performance limitations in today's chip designs is clock skew, the uncertainty in arrival times between a pair of cl...
| Autor principal: | |
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| Formato: | Libro electrónico |
| Idioma: | Inglés |
| Publicado: |
San Francisco :
Morgan Kaufmann Publishers
c2001.
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| Edición: | 1st edition |
| Colección: | Morgan Kaufmann Series in Computer Architecture and Design
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| Materias: | |
| Ver en Biblioteca Universitat Ramon Llull: | https://discovery.url.edu/permalink/34CSUC_URL/1im36ta/alma991009627108506719 |
| Sumario: | As advances in technology and circuit design boost operating frequencies of microprocessors, DSPs and other fast chips, new design challenges continue to emerge. One of the major performance limitations in today's chip designs is clock skew, the uncertainty in arrival times between a pair of clocks. Increasing clock frequencies are forcing many engineers to rethink their timing budgets and to use skew-tolerant circuit techniques for both domino and static circuits. While senior designers have long developed their own techniques for reducing the sequencing overhead of domino circuits, th |
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| Notas: | Description based upon print version of record. |
| Descripción Física: | 1 online resource (239 p.) |
| Bibliografía: | Includes bibliographical references and index. |
| ISBN: | 9781281078049 9786611078041 9780080541266 |
