Skew-tolerant circuit design
As advances in technology and circuit design boost operating frequencies of microprocessors, DSPs and other fast chips, new design challenges continue to emerge. One of the major performance limitations in today's chip designs is clock skew, the uncertainty in arrival times between a pair of cl...
| Autor principal: | |
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| Formato: | Libro electrónico |
| Idioma: | Inglés |
| Publicado: |
San Francisco :
Morgan Kaufmann Publishers
c2001.
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| Edición: | 1st edition |
| Colección: | Morgan Kaufmann Series in Computer Architecture and Design
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| Materias: | |
| Ver en Biblioteca Universitat Ramon Llull: | https://discovery.url.edu/permalink/34CSUC_URL/1im36ta/alma991009627108506719 |
Tabla de Contenidos:
- Front Cover; Skew-Tolerant Circuit Design; Copyright Page; Contents; Preface; Chapter 1. Introduction; 1.1 Overhead in Flip-Flop Systems; 1.2 Throughput and Latency Trends; 1.3 Skew-Tolerant Static Circuits; 1.4 Domino Circuits; 1.5 Case Studies; 1.6 A Look Ahead; 1.7 Exercises; Chapter 2. Static Circuits; 2.1 Preliminaries; 2.2 Static Memory Elements; 2.3 Memory Element Design; 2.4 Historical Perspective; 2.5 Summary; 2.6 Exercises; Chapter 3. Domino Circuits; 3.1 Skew-Tolerant Domino Timing; 3.2 Domino Gate Design; 3.3 Historical Perspective; 3.4 Summary; 3.5 Exercises
- Chapter 4. Circuit Methodology4.1 Static/Domino Interface; 4.2 Clocked Element Design; 4.3 Testability; 4.4 Historical Perspective; 4.5 Summary; 4.6 Exercises; Chapter 5. Clocking; 5.1 Clock Waveforms; 5.2 Skew-Tolerant Domino Clock Generation; 5.3 Summary; 5.4 Exercises; Chapter 6. Timing Analysis; 6.1 Timing Analysis without Clock Skew; 6.2 Timing Analysis with Clock Skew; 6.3 Extension to Flip-Flops and Domino Circuits; 6.4 Min-Delay; 6.5 A Verification Algorithm; 6.6 Case Study; 6.7 Historical Perspective; 6.8 Summary; 6.9 Exercises; Chapter 7. Conclusions; Appendix A: Timing Constraints
- Appendix B: Solutions to Even-Numbered ExercisesBibliography; Index; About the Author
