Advances in embedded and fan-out wafer level packaging technologies
Examines the advantages of Embedded and FO-WLP technologies, potential application spaces, package structures available in the industry, process flows, and material challenges Embedded and fan-out wafer level packaging "FO-WLP" technologies have been developed across the industry over the...
| Otros Autores: | , |
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| Formato: | Libro electrónico |
| Idioma: | Inglés |
| Publicado: |
Hoboken, New Jersey, USA :
John Wiley & Sons, Inc
2019.
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| Edición: | First edition |
| Colección: | THEi Wiley ebooks.
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| Materias: | |
| Ver en Biblioteca Universitat Ramon Llull: | https://discovery.url.edu/permalink/34CSUC_URL/1im36ta/alma991009631528806719 |
Tabla de Contenidos:
- Preface xvii
- List of Contributors xxiii
- Acknowledgments xxvii
- 1 History of Embedded and Fan-Out Packaging Technology 1 /Michael Topper, Andreas Ostmann, Tanja Braun, and Klaus-Dieter Lang
- 2 FO-WLP Market and Technology Trends 39 /E. Jan Vardaman
- 3 Embedded Wafer-Level Ball Grid Array (eWLB) Packaging Technology Platform 55 /Thorsten Meyer and Steffen Krohnert
- 4 Ultrathin 3D FO-WLP eWLB-PoP (Embedded Wafer-Level Ball Grid Array-Package-on-Package) Technology 77 /S.W. Yoon
- 5 NEPES’ Fan-Out Packaging Technology from Single die, SiP to Panel-Level Packaging 97 /Jong Heon (Jay) Kim
- 6 M-Series Fan-Out with Adaptive Patterning 117 /Tim Olson and Chris Scanlan
- 7 SWIFTR Semiconductor Packaging Technology 141 /Ron Huemoeller and Curtis Zwenger
- 8 Embedded Silicon Fan-Out (eSiFOR) Technology for Wafer-Level System Integration 169 /Daquan Yu
- 9 Embedding of Active and Passive Devices by Using an Embedded Interposer: The i2 Board Technology 185 /Thomas Gottwald, Christian Roessle, and Alexander Neumann
- 10 Embedding of Power Electronic Components: The Smart p2 Pack Technology 201 /Thomas Gottwald and Christian Roessle
- 11 Embedded Die in Substrate (Panel-Level) Packaging Technology 217 /Tomoko Takahashi and Akio Katsumata
- 12 Blade: A Chip-First Embedded Technology for Power Packaging 241 /Boris Plikat and Thorsten Scharf
- 13 The Role of Liquid Molding Compounds in the Success of Fan-Out Wafer-Level Packaging Technology 261 /Katsushi Kan, Michiyasu Sugahara, and Markus Cichon
- 14 Advanced Dielectric Materials (Polyimides and Polybenzoxazoles) for Fan-Out Wafer-Level Packaging (FO-WLP) 271 /T. Enomoto, J.I. Matthews, and T. Motobe
- 15 Enabling Low Temperature Cure Dielectrics for Advanced Wafer-Level Packaging 317 /Stefan Vanclooster and Dimitri Janssen
- 16 The Role of Pick and Place in Fan-Out Wafer-Level Packaging 347 /Hugo Pristauz, Alastair Attard, and Harald Meixner
- 17 Process and Equipment for eWLB: Chip Embedding by Molding 371 /Edward Furgut, Hirohito Oshimori, and Hiroaki Yamagishi.
- 18 Tools for Fan-Out Wafer-Level Package Processing 403 /Nelson Fan, Eric Kuah, Eric Ng, and Otto Cheung
- 19 Equipment and Process for eWLB: Required PVD/Sputter Solutions 419 /Chris Jones, Ricardo Gaio, and Jose Castro
- 20 Excimer Laser Ablation for the Patterning of Ultra-fine Routings 441 /Habib Hichri, Markus Arendt, and Seongkuk Lee
- 21 Temporary Carrier Technologies for eWLB and RDL-First Fan-Out Wafer-Level Packages 457 /Thomas Uhrmann and Boris Povazay
- 22 Encapsulated Wafer-Level Package Technology (eWLCSP): Robust WLCSP Reliability with Sidewall Protection 471 /S.W. Yoon
- 23 Embedded Multi-die Interconnect Bridge (EMIB): A Localized, High Density, High Bandwidth Packaging Interconnect 487 /Ravi Mahajan, Robert Sankman, Kemal Aygun, Zhiguo Qian, Ashish Dhall, Jonathan Rosch, Debendra Mallik, and Islam Salama
- 24 Interconnection Technology Innovations in 2.5D Integrated Electronic Systems 501 /Paragkumar A. Thadesar, Paul K. Jo, and Muhannad S. Bakir
- References 515
- Index 521.
