Formal verification : an essential toolkit for modern VLSI design

Formal verification an essential toolkit for modern VLSI design

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Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice for working engineers integrating these techniques into their work. Building on a basic knowledge of System Verilog, this book demystifies FV and present...

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Detalles Bibliográficos
Otros Autores: Seligman, Erik, author (author), Schubert, Tom, author (cover designer), Kumar, M. V. Achutha Kiran, author, Studholme, Alan, cover designer
Formato: Libro electrónico
Idioma:Inglés
Publicado: Amsterdam, [Netherlands] : Morgan Kaufmann 2015.
Edición:1st edition
Materias:
Electronic circuits > Testing.
Integrated circuits > Very large scale integration > Design and construction.
Verilog (Computer hardware description language)
Ver en Biblioteca Universitat Ramon Llull:https://discovery.url.edu/permalink/34CSUC_URL/1im36ta/alma991009629570406719

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