Formal verification an essential toolkit for modern VLSI design
Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice for working engineers integrating these techniques into their work. Building on a basic knowledge of System Verilog, this book demystifies FV and present...
Otros Autores: | , , , |
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Formato: | Libro electrónico |
Idioma: | Inglés |
Publicado: |
Amsterdam, [Netherlands] :
Morgan Kaufmann
2015.
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Edición: | 1st edition |
Materias: | |
Ver en Biblioteca Universitat Ramon Llull: | https://discovery.url.edu/permalink/34CSUC_URL/1im36ta/alma991009629570406719 |
Sumario: | Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice for working engineers integrating these techniques into their work. Building on a basic knowledge of System Verilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. The text prepares readers to effectively introduce FV in their organization and deploy FV techniques to increase design and validation productivity. Presents formal verific |
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Notas: | Description based upon print version of record. |
Descripción Física: | 1 online resource (372 p.) |
Bibliografía: | Includes bibliographical references at the end of each chapters and index. |
ISBN: | 9780128008157 9780128007273 |