Architecture design for soft errors
This book provides a comprehensive description of the architetural techniques to tackle the soft error problem. It covers the new methodologies for quantitative analysis of soft errors as well as novel, cost-effective architectural techniques to mitigate them. To provide readers with a better grasp...
| Autor principal: | |
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| Formato: | Libro electrónico |
| Idioma: | Inglés |
| Publicado: |
Amsterdam ; Boston :
Morgan Kaufmann Publishers/Elsevier
c2008.
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| Edición: | 1st edition |
| Materias: | |
| Ver en Biblioteca Universitat Ramon Llull: | https://discovery.url.edu/permalink/34CSUC_URL/1im36ta/alma991009627483106719 |
Tabla de Contenidos:
- Front Cover; Architecture Design for Soft Errors; Copyright Page; Table of Contents; Foreword; Preface; Chapter 1. Introduction; 1.1 Overview; 1.2 Faults; 1.3 Errors; 1.4 Metrics; 1.5 Dependability Models; 1.6 Permanent Faults in Complementary Metal Oxide Semiconductor Technology; 1.7 Radiation-Induced Transient Faults in CMOS Transistors; 1.8 Architectural Fault Models for Alpha Particle and Neutron Strikes; 1.9 Silent Data Corruption and Detected Unrecoverable Error; 1.10 Soft Error Scaling Trends; 1.11 Summary; 1.12 Historical Anecdote; References
- Chapter 2. Device and Circuit-Level Modeling Measurement and Mitigation2.1 Overview; 2.2 Modeling Circuit-Level SERs; 2.3 Measurement; 2.4 Mitigation Techniques; 2.5 Summary; 2.6 Historical Anecdote; References; Chapter 3. Architectural Vulnerability Analysis; 3.1 Overview; 3.2 AVF Basics; 3.3 Does a Bit Matter?; 3.4 SDC and DUE Equations; 3.5 ACE Principles; 3.6 Microarchitectural Un-ACE Bits; 3.7 Architectural Un-ACE Bits; 3.8 AVF Equations for a Hardware Structure; 3.9 Computing AVF with Little's Law; 3.10 Computing AVF with a Performance Model
- 3.11 ACE Analysis Using the Point-of-Strike Fault Model3.12 ACE Analysis Using the Propagated Fault Model; 3.13 Summary; 3.14 Historical Anecdote; References; Chapter 4. Advanced Architectural Vulnerability Analysis; 4.1 Overview; 4.2 Lifetime Analysis of RAM Arrays; 4.3 Lifetime Analysis of CAM Arrays; 4.4 Effect of Cooldown in Lifetime Analysis; 4.5 AVF Results for Cache, Data Translation Buffer, and Store Buffer; 4.6 Computing AVFs Using SFI into an RTL Model; 4.7 Case Study of SFI; 4.8 Summary; 4.9 Historical Anecdote; References; Chapter 5. Error Coding Techniques; 5.1 Overview
- 5.2 Fault Detection and ECC for State Bits5.3 Error Detection Codes for Execution Units; 5.4 Implementation Overhead of Error Detection and Correction Codes; 5.5 Scrubbing Analysis; 5.6 Detecting False Errors; 5.7 Hardware Assertions; 5.8 Machine Check Architecture; 5.9 Summary; 5.10 Historical Anecdote; References; Chapter 6. Fault Detection via Redundant Execution; 6.1 Overview; 6.2 Sphere of Replication; 6.3 Fault Detection via Cycle-by-Cycle Lockstepping; 6.4 Lockstepping in the Hewlett-Packard NonStop Himalaya Architecture; 6.5 Lockstepping in the IBM Z-series Processors
- 6.6 Fault Detection via RMT6.7 RMT in the Marathon Endurance Server; 6.8 RMT in the Hewlett-Packard NonStop® Advanced Architecture; 6.9 RMT Within a Single-Processor Core; 6.10 RMT in a Multicore Architecture; 6.11 DIVA: RMT Using Specialized Checker Processor; 6.12 RMT Enhancements; 6.13 Summary; 6.14 Historical Anecdote; References; Chapter 7. Hardware Error Recovery; 7.1 Overview; 7.2 Classification of Hardware Error Recovery Schemes; 7.3 Forward Error Recovery; 7.4 Backward Error Recovery with Fault Detection before Register Commit
- 7.5 Backward Error Recovery with Fault Detection before Memory Commit
